In a semiconductor device in which an IGBT and a free wheel diode (hereinafter called FWD) connected in parallel with each other are formed within the single semiconductor substrate, there is formerly a structure in which a trench burying an insulator therein is formed between an IGBT area for forming a semiconductor area belonging to IGBT and a diode area for forming a semiconductor area belonging to the diode among the semiconductor substrate. The device is disclosed in, e.g., JP-A-2002-314082 (corresponding to U.S. Pat. No. 6,639,295).
As can be seen from a description in which the trench is formed so as to be deeper than an anode area of the diode from a surface side of the semiconductor substrate, this is a technique for restraining the movement of a carrier on the surface side of the semiconductor substrate and reducing an interference of IGBT and the diode.
When an IGBT of a punch through type and a FWD connected in parallel with each other are formed within the single semiconductor substrate, it has been found that a problem explained below is caused.
FIG. 14 shows a cross-sectional view of the semiconductor device of a structure considered by the present inventors as a comparison of the present disclosure. In FIG. 14, a sectional structure and an equivalent circuit of this semiconductor device are shown together, and the same reference numerals as FIG. 1 are given to constructional portions similar to those of FIG. 1.
In the semiconductor device shown in FIG. 14, IGBT of the punch through type and FWD connected in parallel with each other are formed within the single semiconductor substrate 1. This IGBT is a longitudinal type and is also an N-channel type.
In the semiconductor substrate 1 within FIG. 14, an area for forming plural semiconductor areas constituting the IGBT is an IGBT area, and an area for forming plural semiconductor areas constituting the FWD is an FWD area. Concretely, a P+ type collector area 2, N type layers 3, 3a, an N− type layer 4, a P type base area 5 and an N+ type emitter area 6 constituting IGBT are formed in the IGBT area. A gate electrode 8 buried within a trench 7 is formed in the P type base area 5 of the IGBT area. Further, an N+ type area 9, N type layers 3, 3b, an N− type layer 4 and a P type area 10 constituting FWD are formed in the FWD area.
N type layers 3a, 3b, 3 among these areas and layers are areas higher in impurity concentration than the N− type layer 4, and function as a field stopper layer (hereinafter called an FS layer) for preventing that the spread of a depletion layer at a bias time between the collector and the emitter reaches the P+ type collector area 2.
Further, a single electrode 11 of a shape formed by continuing an emitter electrode (E) 11a of IGBT and an anode electrode (A) 11b of FWD is formed on the surface of the semiconductor substrate 1. A single electrode 12 of a shape formed by continuing a collector electrode (C) 12a of IGBT and a cathode electrode (K) 12b of FWD is formed on the rear face of the semiconductor substrate 1.
In the semiconductor device of such a structure, when an N channel 5a is formed in a rear face side diode 31 located on the rear face side of the semiconductor substrate 1 in the IGBT area, i.e., in a portion adjacent to the gate electrode 8 of the P type base area 5, it attains a structure in which a cathode (FS layer 3a) and an anode (collector electrode 12a) of the PN junction diode 31 constructed by P+ type area 2, N type layer 3, N− type layer 4, N channel 5a and N+ type area 6 are short-circuited through the N type FS layer 3b of the FWD area, the N+ type area 9 and the cathode electrode 12b between the collector and the emitter.
At this time, when an electronic electric current from an IGBT channel located on the surface side of the semiconductor substrate 1 is flowed to the rear face electrode 12 of the semiconductor substrate 1 through the N− type layer 4 within the IGBT area, the N− type layer 4 of the FWD area, the N type FS layer 3 and the N+ type area 9, a resistance component of the N− type layer 4 is set to R1. When the electronic electric current from the IGBT channel is flowed to the rear face electrode 12 of the semiconductor substrate 1 through the N− type layer 4 and the N type FS layer 3a of the IGBT area, and the N type FS layer 3b and the N+ type area 9 of the FWD area, a resistance component of the N type FS layer 3 of the IGBT area and the FWD area is set to R2. In this case, R1>R2 is attained.
Therefore, as shown by an arrow within FIG. 14, the electronic electric current from the IGBT channel is flowed away to the collector electrode 12a through the N type FS layer 3b of the FWD area and the N+ type area 9.
Here, FIG. 15 shows I-V characteristics of the semiconductor device shown in FIG. 14 (characteristics of the collector electric current and the voltage between the collector and the emitter).
In the IGBT within the semiconductor device shown in FIG. 14, as originally shown by a broken line within FIG. 15, the collector electric current begins to be flowed when the voltage value between the collector and the emitter exceeds a predetermined voltage, e.g., 0.6V. Namely, the rear face side diode of IGBT is turned on, and IGBT is operated.
However, in the semiconductor device shown in FIG. 14, as mentioned above, the anode and the cathode of the rear face side diode 31 of the IGBT area are short-circuited. Therefore, as shown by a solid line within FIG. 15, even when the voltage value between the collector and the emitter (the voltage value of an external voltage) is increased from 0V, it is difficult that the voltage value substantially applied to the rear face side diode 31 of IGBT reaches 0.6V. Accordingly, it is delayed that the collector electric current begins to be flowed. When the electronic electric current from the IGBT channel is flowed to the rear face side electrode 12 through the N type layer 3 of the IGBT area and the FWD area so that an I×R drop in its electronic electric current path, i.e., the voltage applied to the rear face side diode 31 reaches 0.6V, the collector electric current finally begins to be flowed. Thereafter, it is returned to an original behavior. In the following description, a portion (a bent portion within I-V line) 32 surrounded by a one-dotted chain line showing a behavior different from that of a broken line among the solid line within FIG. 15 is called a snap back.
Thus, in the semiconductor device of the structure shown in FIG. 14, a problem exists in that it is difficult to forward bias the rear face side diode 31 by the external voltage, and no hole implantation from the rear face electrode 12 side is promoted, and the snap back is formed in IGBT on-characteristics.
In the semiconductor device shown in FIG. 14, the FS layer 3 is also formed in the FWD area. However, the above problem is caused in the semiconductor device in which the diode and IGBT of the punch through type having the N type FS layer 3a higher in impurity concentration than the N− type layer 4 are formed in the single semiconductor substrate 1 irrespective of whether the FS layer 3 is formed in the FWD area or not. Thus, it is required to reduce generation of the snap back.